The present application relates to semiconductor technology. More particularly, the present application relates to a method of forming a semiconductor structure including a stack of suspended III-V or germanium semiconductor nanowires that are formed utilizing a lateral epitaxial growth process. The present application also relates to a semiconductor structure that includes such a stack of suspended III-V or germanium semiconductor nanowires.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (finFETs) or gate-all-around semiconductor nanowire field effect transistors is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Such non-planar semiconductor devices can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs.
Gate-all-around semiconductor nanowire field effect transistors provide superior electrostatics and higher current density per footprint than finFET devices. Gate-all-around semiconductor nanowire field effect transistors include at least one semiconductor nanowire including a source region, a drain region and a channel region located between the source region and the drain region, and a gate electrode that wraps around the channel region of the at least one semiconductor nanowire. A gate dielectric is typically disposed between the channel region of the at least one semiconductor nanowire and the gate electrode. The gate electrode regulates electron flow through the semiconductor nanowire channel between the source region and the drain region. Stacked semiconductor nanowires, in which the semiconductor nanowires are formed one atop another, afford higher density than their non-stacked semiconductor nanowire counterparts.
However, there are many process challenges which must be overcome in order to facilitate a gate-all-around semiconductor nanowire field effect transistor that contains stacked semiconductor nanowires. For example, there is a need for providing a gate-all-around semiconductor nanowire field effect transistor in which a stack of a III-V or germanium (Ge) channel material is employed since such channel materials have high mobility for electrons and holes as compared with silicon (Si) channel materials.